Lithography method and device

ABSTRACT

Lithography methods and devices are shown that include a semiconductor structure such as a mask. Methods and devices are shown that include a pattern of mask features and a composite feature. Selected mask features include doubled mask features. Methods and devices shown may provide varied feature sizes (including sub-resolution) with a small number of processing steps.

PRIORITY APPLICATION

This application is a divisional of U.S. application Ser. No.13/192,117, filed Jul. 27, 2011, which is incorporated herein byreference in its entirety.

TECHNICAL FIELD

Various embodiments described herein relate to apparatus, systems, andmethods associated with lithography, for example patterning and printingfeatures in the manufacture of semiconductor components.

BACKGROUND

Photolithography is a fabrication technique that is employed for use ina number of industries, including the semiconductor processing industry.Specifically, photolithography uses an energy source such as ultraviolet(UV) light, x-ray wavelength, other wavelengths of radiation, etc. toexpose selected regions of a surface. In one common technique, thesurface includes a semiconductor wafer such as silicon that has beencoated with a resist material. The resist material properties arelocally changed when exposed to the energy source, which allows selectedregions of the resist material to remain, while unwanted regions of theresist material are removed.

In one method of photolithography, a pattern of features is created on areticle or mask, and the pattern on the reticle is focused onto asemiconductor surface using optics that adjust the scale of the patternon the reticle to fit the semiconductor surface. In the semiconductorindustry, there is an ever present pressure to reduce the size offeatures in the pattern to increase the density of patterned featurespacked into the same semiconductor surface area. In one exampleindustry, manufacturers of random access memory chips such as dynamicrandom access memory (DRAM) strive to put more storage cells onto asingle chip.

As feature size decreases, photolithography of smaller and smallerfeatures becomes more and more difficult. Methods and devices are neededthat provide smaller features and improve process efficiency.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a lithography system according to an embodiment of theinvention.

FIG. 2A-2G show processing operations to form a semiconductor structureaccording to an embodiment of the invention.

DETAILED DESCRIPTION

In the following detailed description of the invention, reference ismade to the accompanying drawings that form a part hereof and in whichare shown, by way of illustration, specific embodiments in which theinvention may be practiced. These embodiments are described insufficient detail to enable those skilled in the art to practice theinvention. Other embodiments may be utilized and logical, optical,material changes, etc. may be made.

The term “horizontal” as used in this application is defined as a planeparallel to the conventional plane or surface of a substrate, such as awafer or die, regardless of the orientation of the substrate. The term“vertical” refers to a direction perpendicular to the horizontal asdefined above. Prepositions, such as “on”, “side” (as in “sidewall”),“higher”, “lower”, “over” and “under” are defined with respect to theconventional plane or surface being on the top surface of the substrate,regardless of the orientation of the substrate. The following detaileddescription is, therefore, not to be taken in a limiting sense, and thescope of the present invention is defined only by the appended claims,along with the full scope of equivalents to which such claims areentitled.

FIG. 1 shows a system where a pattern of features is formed on a reticleand the pattern is then transferred to a substrate by means ofphotolithography. In one embodiment the pattern of features includessemiconductor device component features, including, but not limited to,source/drain regions, transistor gates, trace lines, source/draincontacts, vias, capacitor plates, etc. FIG. 1 shows a photolithographysystem 100 according to an embodiment of the invention. The system 100includes a substrate 110. In one embodiment, the substrate 110 includesa semiconductor substrate, such as a silicon wafer. Although asemiconductor substrate is discussed for illustration, embodiments ofthe invention will comprise other working surfaces utilizingphotolithography.

A resist material 120 is located over a surface of the substrate 110. Areticle 130 is shown with an aperture 132, and is spaced apart from theresist material 120 by a focal length. The reticle 130 is shown in asimplified form with an energy blocking region and an aperture 132. Inone embodiment, the reticle 130 further includes a material that issubstantially transparent, such as a glass. In one embodiment, thereticle 130 further includes an attenuated and partly opaque portionadapted to block a portion of an energy source 140 or to phase shift aportion of the energy source 140. The terms “transparent”, “attenuated”,“partly opaque” and other associated optical terms in the presentspecification refer to optical properties of the reticle 130. Possibleenergy sources include, but are not limited to, UV radiation and x-rayradiation. One source of suitable energy is from a laser light source.

The energy source 140 is directed toward the resist material 120, with aportion of the energy source 140 being blocked by the reticle 130. Aportion of the energy source 140 is shown passing through the aperture132 in the reticle 130 and toward projection optics 150. Projectionoptics 150 may be utilized to focus and scale the energy source 140 thatpasses through the aperture 132. Projection optics 150 may comprise onelens or up to and more than 40 lens elements. Projection optics 150 maybe used to scale the energy 140 to smaller features than is possiblewith reticle 130 alone, thus allowing focused energy source 145 to writesmaller features onto the resist material 120. The focused energy source145 is shown contacting the resist material 120 in a selected region122. The selected region 122 interacts with the focused energy source145 to selectively alter the resist material properties of resistmaterial 120. Two possible interactions include a curing of the resistmaterial and a weakening of the resist material. In one possibility, theresist material 120 in the selected region 122 is cured and remainswhile the non-selected region of the resist material 120 is removed. Inanother possibility, the resist material 120 in the selected region 122is weakened and is removed while the non-selected region of the resistmaterial remains.

New techniques in the semiconductor industry are constantly beingdeveloped to print smaller and smaller features, however, frequentlyvery small features must be printed in a separate processing operationfrom larger features. Printing features of different sizes in more thanone processing operation adds cost to fabrication, and the additionalprocessing steps increase the possibility of additional manufacturingyield loss. Methods that reduce a number of processing operations areneeded.

FIGS. 2A-2G show processing operations to form a semiconductor structureaccording to an embodiment of the invention. The Figures are shown in asimplified cross section, and are not necessarily to scale. FIG. 2Ashows a number of mask features 200 on a substrate 202. In one example,the substrate 202 includes a semiconductor substrate, such as silicon,germanium, gallium arsenide, etc. In one example, the mask features 200are formed using lithography from a first mask material of thickness212. In one example the first mask material is a resist material.

The mask features 200 include a first feature 210 and a second feature220. As shown in the Figure, in one example, both the first feature 210,and the second feature 220 have a thickness 212 measured from thesubstrate 202 to their highest point. A number of spaces 204 are shownwhere the first mask material has been removed (e.g. in a lithographyoperation).

FIG. 2A further shows a recess 222 in the second feature 220. In oneexample, as illustrated in FIG. 2A, a number of recesses 222 areincluded within the second feature 220. In one example, the recess 222is formed during the same lithography process as the number of spaces204. The recess 222 is formed to a depth 2224 through only a portion ofthe thickness 212 of the first mask material. In one example, asub-resolution feature is used to form the recess 222. A sub-resolutionfeature may not allow enough of an energy source (e.g. energy source140) through a reticle (e.g. reticle 130) to form a space all the waythrough the thickness 212 of the first mask material.

In one embodiment, the number of mask features 200 may be furtherprocessed in a trimming operation. FIG. 2B shows the number of maskfeatures 200 after an example trimming operation. The first features 110are reduced from their original width to a trimmed width 214. In oneexample, a trimming operation includes an etch, or other removal processthat reduces width 214, yet leaves the number of mask features 200 inplace. In addition to reducing width 214, a trimming operation may alsosharpen corners of the number of mask features 200.

In embodiments using a trimming operation, the recesses 222 of thesecond feature 220 may be deepened from depth 224 to a depth 228 andwidened to a width 230. A number of full thickness portions 225 may alsobe reduced to a width 226.

FIG. 2C shows the number of mask features 200 with a second maskmaterial 240 deposited over the number of mask features 200. In oneexample, the second mask material 240 includes a hardmask material. Oneexample of a hardmask material includes amorphous carbon or a lowtemperature dielectric (e.g. ALD Oxide). FIG. 2C shows the second maskmaterial 240 deposited to a thickness 242. In one example, the thickness242 is substantially consistent over the number of mask features 200 andthe substrate 202.

FIG. 2C shows the recesses 222 filled with the second mask material 240.In one example, the width 230 of the recesses 222 is such that thesecond mask material 240 builds up within the recesses 222 to athickness 228 that is greater than the thickness 242 of the second maskmaterial 240 in other locations.

FIG. 2D shows the number of mask features 200 after a selective removaloperation. A portion of the second mask material 240 has been removed,leaving behind sidewall portions 250 and protective portions 252 withinthe recesses 222. In one example, the selective removal operationincludes an anisotropic removal operation that preferentially removesone portion of the second mask material 240 more quickly than otherportions. For example, FIG. 2D illustrates an operation where horizontalportions of the second mask material 240 are removed, leaving verticalportions behind. In one example, the selective removal operationincludes a directional etch operation. In one example the selectiveremoval operation includes a plasma removal operation.

In one example, protective portions 252 remain, while other horizontalportions of the second mask material 240 are removed in part because ofthe increased thickness 228 within the recesses 222. In one example,corners 254 of remaining portions of the second mask material 240 may berounded.

In FIG. 2D, the first feature 210 and the second feature 220 remain,with the sidewall portions 250 and protective portions 252 forminginterfaces with various parts of the first feature 210 and the secondfeature 220. As recited above, the first feature 210 and the secondfeature 220 are formed from a first mask material, while the sidewallportions 250 and protective portions 252 are formed from a second maskmaterial. In one example, the first mask material and the second maskmaterial are selective to removal processes such that, for example, thefirst mask material is removable while leaving the second mask materialsubstantially whole.

FIG. 2E shows the substrate 202 after a selective removal process of thefirst mask material. The sidewall portions 250 are left behind, forminga second pattern of mask features 260. In one example, the secondpattern of mask features 260 form a doubled pattern, where two sidewallsof a single first feature 210 are used to form two second features 260.In addition to the economy of forming two features 260 for every singlefirst feature 210, examples as described above may be used to form asecond pattern of mask features 260 that are all much smaller than thefirst feature 210. A width of the second features 260 is dictated onlyby deposition thickness 242, not by limitations of energetic wavelengthas in the lithography used to form the first feature 210.

FIG. 2E further shows a composite feature 262 formed by embodiments ofthe present disclosure. The composite feature 262 includes a firstmaterial portion 221 formed from the second feature 220. The firstmaterial portion 221 forms an interface with the substrate 202. Thecomposite feature 262 also includes the protective portions 252 from theoperation described in FIG. 2D. The protective portions 252 form aninterface with the first material portion 221.

In one example, first material portion 221 is not removed during thefirst material removal operation due to the protective portions 252 atleast partially shielding the first material portion 221. In oneexample, a small portion 234 of the second feature 220 is removed,however due to the small width 226 of full thickness portions 225, andthe protective portions 252, a part of the second feature 220 remainsprotected.

In one example, a semiconductor structure including the second patternof mask features 260 and the composite feature 262 are formedsubstantially concurrently. Forming a pattern of sub-resolutionfeatures, such as the second pattern of mask features 260 at the sametime as a larger feature such as the composite feature 262 providesvaried feature sizes, with a small number of processing steps. Fewerprocessing steps reduces complexity and cost of manufacturing.

FIG. 2F illustrates a processing operation using a semiconductorstructure such as a mask with the second pattern of mask features 260and the composite feature 262 from FIG. 2E. In the example of FIG. 2F, alayer of material 270 is deposited, however the invention is not solimited. Other operations may include ion implanting, doping, etching,or other semiconductor processing operations using a mask.

FIG. 2G illustrates an example of resulting features 271 from theprocess of FIG. 2F. In one example, the features 271 include linearfeatures such as electrical transmission lines, for example, lines tointerconnect memory cells in a memory device. A first number of features272 in the resulting features 271 may include features separated bysub-resolution spaces 273, while other features 274 are larger thatfeatures 272, and separated by larger spaces 275.

While a number of embodiments of the invention are described, the abovelists are not intended to be exhaustive. Although specific embodimentshave been illustrated and described herein, it will be appreciated bythose of ordinary skill in the art that any arrangement that iscalculated to achieve the same purpose may be substituted for thespecific embodiment shown. This application is intended to cover anyadaptations or variations of embodiments of the present invention. It isto be understood that the above description is intended to beillustrative and not restrictive. Combinations of the above embodiments,and other embodiments, will be apparent to those of skill in the artupon studying the above description.

What is claimed is:
 1. A semiconductor structure, comprising: a numberof first masking structures formed from a first material, the number offirst masking structures forming a direct interface with a substrate; acomposite masking structure, including: a second material forming adirect interface with the substrate; a protective portion including,side structures forming a direct interface with sides of the secondmaterial, the side structures formed from the first material, and one ormore recesses in the second material, with the first material at leastpartially filing the one or more recesses.
 2. The semiconductorstructure of claim 1, wherein the first material includes a resistmaterial.
 3. The semiconductor structure of claim 1, wherein the secondmaterial includes a hardmask material.
 4. The semiconductor structure ofclaim 3, wherein the hardmask material includes amorphous carbon.
 5. Alithographic pattern on a semiconductor substrate, comprising: acomposite masking structure, including: a first mask material forming adirect interface with the semiconductor substrate; a number of recessesformed within the first mask material; and a second mask materialdifferent from the first mask material, formed over the first maskmaterial, and within the number of recesses.
 6. The lithographic patternof claim 5, wherein the composite masking structure further includes endportions that form a direct interface with the semiconductor substrateand abut sides of the first mask material.
 7. The lithographic patternof claim 5, wherein the number of recesses are sub-lithographic.
 8. Thelithographic pattern of claim 5, wherein the first mask material is aresist material.
 9. The lithographic pattern of claim 5, wherein thesecond mask material is a hardmask material.
 10. The lithographicpattern of claim 9, wherein the hardmask includes amorphous carbon. 11.The lithographic pattern of claim 9, wherein the hardmask includes anoxide material.
 12. The lithographic pattern of claim 5, furtherincluding a number of non-composite masking structures as part of thepattern.
 13. A lithographic pattern on a semiconductor substrate,comprising: a number of doubled lithographic features; a compositemasking structure, including: a first mask material forming a directinterface with the semiconductor substrate; a number of recesses formedwithin the first mask material; and a second mask material formed overthe first mask material, and within the number of recesses.
 14. Thelithographic pattern of claim 13, wherein the number of doubled featuresare formed from the second mask material.
 15. The lithographic patternof claim 13, wherein the number of doubled features are formed from ahardmask material.
 16. The lithographic pattern of claim 13, whereinboth the doubled lithographic features and the number of recesses aresub-lithographic.
 17. The lithographic pattern of claim 13, wherein thecomposite masking structure further includes end portions that form adirect interface with the semiconductor substrate and abut sides of thefirst mask material.
 18. The lithographic pattern of claim 17, whereinthe end portions are formed from the second mask material.